`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:25:34 05/04/2013
// Design Name:   Processor
// Module Name:   T:/Lab3/tb_Processor.v
// Project Name:  Lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Processor
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_Processor;

	// Inputs
	reg pop_data;
	reg [7:0] data_in;
	reg read;
	reg clk;

	// Outputs
	wire [3:0] data_out;

	// Instantiate the Unit Under Test (UUT)
	Processor uut (
		.pop_data(pop_data), 
		.data_in(data_in), 
		.read(read), 
		.clk(clk),
		.data_out(data_out)
	);

	initial begin
		// Initialize Inputs
		pop_data = 0;
		data_in = 0;
		read = 0;
		clk = 0;
		
		forever #10 clk = ~clk;

		// Wait 100 ns for global reset to finish
		#100;	

	end
	
	initial begin
		// Add stimulus here
		data_in <= 8'b01110000;
		pop_data <= 1'b1;
		
		#40;
		pop_data <= 1'b0;
		
		#80;
		data_in <= 8'b01110100;
		pop_data <= 1'b1;
		
		#40;
		pop_data <= 1'b0;
		
		#80;
		data_in <= 8'b01000001;
		pop_data <= 1'b1;
		
		#40;
		pop_data <= 1'b0;
		
		#80;
		read <= 1'b1;
		
		#40;
		read <= 1'b0;
		
		#80;
		data_in <= 8'b01011000;
		pop_data <= 1'b1;
		
		#40;
		pop_data <= 1'b0;
		
		#80;
		data_in <= 8'b10101100;
		pop_data <= 1'b1;
		
		#40;
		pop_data <= 1'b0;
		
		#80;
		data_in <= 8'b11101110;
		pop_data <= 1'b1;
		
		#40;
		pop_data <= 1'b0;
		
	end
      
endmodule

